| Presentation | 1998/10/15 A High-Performance Set-Associative Cache Architecture with Speculative Way-Selection Koji Inoue, Tohru Ishihara, Kazuaki Murakami, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have proposed a novel cache architecture for performance/energy efficiency, called"way-predictable set-associative cache(or way-predictable cache)". In general, conventional set-associative caches have several ways, and a only way is selected based on the result of tag comparisons. This process makes the cache access time longer. On the other hand, the way-predictable cache predicts a way having a data which will be referenced by the processor before tag comparisons. So, access speed of the way-predictable cache is faster than that of conventional set-associative caches due to the specurative way-selection. The way-predictable cache can achieve fast access just like direct-mapped caches, at the same time, higher hit rate is maintained due to set-associative method. We have quantitatively evaluated the way-predictable cache with many benchmarks. As the results, it is observed that the performance improvement achieved by an way-predictable cache is about 20%, compared to a conventional set-associative cache. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high performance / cache / speculation / prediction / way |
| Paper # | DSP98-94,ICD98-181,CPSY98-96 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/10/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A High-Performance Set-Associative Cache Architecture with Speculative Way-Selection |
| Sub Title (in English) | |
| Keyword(1) | high performance |
| Keyword(2) | cache |
| Keyword(3) | speculation |
| Keyword(4) | prediction |
| Keyword(5) | way |
| 1st Author's Name | Koji Inoue |
| 1st Author's Affiliation | Department of Computer Science and Communication Engineering, Kyushu University:A Priori Microsystems, Inc.() |
| 2nd Author's Name | Tohru Ishihara |
| 2nd Author's Affiliation | Department of Computer Science and Communication Engineering, Kyushu University |
| 3rd Author's Name | Kazuaki Murakami |
| 3rd Author's Affiliation | Department of Computer Science and Communication Engineering, Kyushu University:A Priori Microsystems, Inc. |
| Date | 1998/10/15 |
| Paper # | DSP98-94,ICD98-181,CPSY98-96 |
| Volume (vol) | vol.98 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |