Presentation 1998/10/15
16-bit, 0.6-μm CMOS Digital Comparator
A. Hayafune, M. Oh-hashi, T. Enomoto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 16-bit, 0.6-μm CMOS digital comparator, which detected either the minimum or maximum value from data sequence, was developed. It consisted of an input part and a 4-bit comparator tree followed by a decision circuit. Circuit volume of the newly developed 4-bit comparator tree was drastically reduced by a factor of 2. Thus, silicon area of the 16-bit comparator was reduced from 0.0276 mm^2 to 0.0218 mm^2(about 4/5). Both delay time and power dissipation of the 16-bit comparator were also reduced from 6.59 ns and 0.363 mW to 5.56 ns(about 9/10)and 0.293 mW(about 4/5), respectively.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) comparator / silicon area / delay time / power dissipation
Paper # DSP98-91,ICD98-178,CPSY98-93
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Conference Date 1998/10/15(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 16-bit, 0.6-μm CMOS Digital Comparator
Sub Title (in English)
Keyword(1) comparator
Keyword(2) silicon area
Keyword(3) delay time
Keyword(4) power dissipation
1st Author's Name A. Hayafune
1st Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University()
2nd Author's Name M. Oh-hashi
2nd Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University
3rd Author's Name T. Enomoto
3rd Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University
Date 1998/10/15
Paper # DSP98-91,ICD98-178,CPSY98-93
Volume (vol) vol.98
Number (no) 320
Page pp.pp.-
#Pages 6
Date of Issue