Presentation 1998/10/15
A 0.6μm CMOS 16-Pixcel × 16-Line Absolute Difference Accumulator LSI
T. Ohsawa, Y. Nakamura, Y. Sasajima, T. Enomoto,
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Abstract(in English) Power reduction technique for CMOS absolute difference accumulator array LSI for motion estimation has been studied. Power dissipation of CMOS LSIs was reduced to about 1/8 using"snapping-off"algorithm which can reduce the amount of computation of full-search algorithm by a factor of 1/2. A small absolute difference circuit was developed resulting in reduction of both power and silicon area by factors of about 1/2 and 9/10, respectively. Two different types of absolute difference accumulator array incorporating the"snapping-off"algorithm were designed. One is Wallace's tree type and another is a binary tree type. Hardware size and power dissipation of the binary tree type are 52,300 gates and 496 mW, respectively. These of Wallace's tree type are 47,600 gates and 461 mW, respectively, and are about 9/10 those of the binary tree type. A test chip to examine characteristics for both type array was fabricated using 0.6μm CMOS technology. Experimental results agreed well to simulation results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) motion picture compression / MPEG / power dissipation / motion estimation / "snapping-off"algorithm / mean absolute difference
Paper # DSP98-90,ICD98-177,CPSY98-92
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Conference Date 1998/10/15(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 0.6μm CMOS 16-Pixcel × 16-Line Absolute Difference Accumulator LSI
Sub Title (in English)
Keyword(1) motion picture compression
Keyword(2) MPEG
Keyword(3) power dissipation
Keyword(4) motion estimation
Keyword(5) "snapping-off"algorithm
Keyword(6) mean absolute difference
1st Author's Name T. Ohsawa
1st Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University()
2nd Author's Name Y. Nakamura
2nd Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University
3rd Author's Name Y. Sasajima
3rd Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University
4th Author's Name T. Enomoto
4th Author's Affiliation Information & System Engineering Course Graduate School of Science & Engineering Chuo University
Date 1998/10/15
Paper # DSP98-90,ICD98-177,CPSY98-92
Volume (vol) vol.98
Number (no) 320
Page pp.pp.-
#Pages 6
Date of Issue