| Presentation | 1998/6/19 PLT(Partial Low Threshold)-CMOS scheme for low power applications Shoichiro Kashiwakura, Tetsuyoshi Shiota, Wataru Shibamoto, Atsuki Inoue, Ryoichi Ohe, Yusuke Matsunaga, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes the design method using gates which are partially replaced by low Vth transistors. Using dual Vth transistors in a gate, we can achieve a circuit which is faster at low supply voltage and has small leakage current in a stand-by mode without any area penalty. From simulation result of a 16x16b Mac on our 0.25μm Dual Vth CMOS process, total power dissipartion can be reduced by 24% as compared with conventional circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | low power technology / low voltage / leakage currrent / re-mapping / dual vth transistor |
| Paper # | ED98-74,SDM98-74,ICD98-73 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | PLT(Partial Low Threshold)-CMOS scheme for low power applications |
| Sub Title (in English) | |
| Keyword(1) | low power technology |
| Keyword(2) | low voltage |
| Keyword(3) | leakage currrent |
| Keyword(4) | re-mapping |
| Keyword(5) | dual vth transistor |
| 1st Author's Name | Shoichiro Kashiwakura |
| 1st Author's Affiliation | FUJITSU LABORATORIES LIMITED() |
| 2nd Author's Name | Tetsuyoshi Shiota |
| 2nd Author's Affiliation | FUJITSU LABORATORIES LIMITED |
| 3rd Author's Name | Wataru Shibamoto |
| 3rd Author's Affiliation | FUJITSU LABORATORIES LIMITED |
| 4th Author's Name | Atsuki Inoue |
| 4th Author's Affiliation | FUJITSU LABORATORIES LIMITED |
| 5th Author's Name | Ryoichi Ohe |
| 5th Author's Affiliation | FUJITSU LABORATORIES LIMITED |
| 6th Author's Name | Yusuke Matsunaga |
| 6th Author's Affiliation | FUJITSU LABORATORIES LIMITED |
| Date | 1998/6/19 |
| Paper # | ED98-74,SDM98-74,ICD98-73 |
| Volume (vol) | vol.98 |
| Number (no) | 121 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |