Presentation 1998/6/19
Design of Threshold Voltage for Ultra-Low-Voltage CMOS Circuits
Toshishige SHIMAMURA, Takakuni DOUSEKI,
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Abstract(in English) This paper presents a method for design of the threshold voltage for ultra-low-voltage CMOS circuits without speed loss. Equi-speed lines or equi-power lines on a supply voltage and a threshold voltage plane are derived using the analytical equations. We compared the power consumption of the bulk CMOS circuit with the power consumption of the CMOS/SIMOX circuit at a low supply voltage, and also showed the effect of the energy reduction of the MTCMOS/SIMOX circuit. To evaluate the circuit performance of the fundamental logic gates, we designed and fabricated a test chip using 0.25-μm MTCMOS/SIMOX technology. The experimental results corresponded to those of the analysis.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Low Voltage / CMOS / SIMOX / Threshold Voltage / Multi Threshold Voltage
Paper # ED98-73,SDM98-73,ICD98-72
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Conference Date 1998/6/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Threshold Voltage for Ultra-Low-Voltage CMOS Circuits
Sub Title (in English)
Keyword(1) Low Voltage
Keyword(2) CMOS
Keyword(3) SIMOX
Keyword(4) Threshold Voltage
Keyword(5) Multi Threshold Voltage
1st Author's Name Toshishige SHIMAMURA
1st Author's Affiliation NTT System Electronics Laboratories()
2nd Author's Name Takakuni DOUSEKI
2nd Author's Affiliation NTT System Electronics Laboratories
Date 1998/6/19
Paper # ED98-73,SDM98-73,ICD98-72
Volume (vol) vol.98
Number (no) 121
Page pp.pp.-
#Pages 7
Date of Issue