| Presentation | 1998/6/19 A sub-0.1um circuit design with substrate-over-biasing Shigeyoshi Watanabe, Yukihito Oowaki, Mitsuhiro Noguchi, Tuneaki Fuse, Kazumasa Sunouchi, Hitomi Kawaguchiya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The substrate over-biasing technique together with gate-substrate tie technique has been proposed. This circuitry satisfies the highest speed, low leakage current and compatibility with presentry available circuit technologies. With 80nm process technology, 40ps gate delay which correspond to 2GHz operation is achievable at 0.5V supply voltage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 0.5V supply voltage / sub-0.1un device / substrate over-biasing technology |
| Paper # | ED98-72,SDM98-72,ICD98-71 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A sub-0.1um circuit design with substrate-over-biasing |
| Sub Title (in English) | |
| Keyword(1) | 0.5V supply voltage |
| Keyword(2) | sub-0.1un device |
| Keyword(3) | substrate over-biasing technology |
| 1st Author's Name | Shigeyoshi Watanabe |
| 1st Author's Affiliation | Research and Development Center, Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation() |
| 2nd Author's Name | Yukihito Oowaki |
| 2nd Author's Affiliation | Research and Development Center, Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation |
| 3rd Author's Name | Mitsuhiro Noguchi |
| 3rd Author's Affiliation | Research and Development Center, Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation |
| 4th Author's Name | Tuneaki Fuse |
| 4th Author's Affiliation | Research and Development Center, Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation |
| 5th Author's Name | Kazumasa Sunouchi |
| 5th Author's Affiliation | Research and Development Center, Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation |
| 6th Author's Name | Hitomi Kawaguchiya |
| 6th Author's Affiliation | Research and Development Center, Advanced Semiconductor Devices Research Laboratories, Toshiba Corporation |
| Date | 1998/6/19 |
| Paper # | ED98-72,SDM98-72,ICD98-71 |
| Volume (vol) | vol.98 |
| Number (no) | 121 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |