| Presentation | 1998/6/19 5GByte/s Data Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM Takashi Sato, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a 5GByte/s data transfer scheme suitable for synchronous DRAM memory systems. A new, multi-output controlled delay circuit of 30 ps resolution is presented to accomplish a bit-to-bit skew compensation by controlling transmission timing of every data bits. Required improvements in electrical characteristics for higher frequency operation are also presented. Simulated maximum data transfer rate resulted in 5.2/5.9GByte/s(327/370MHz, x64bit, double data rate)for data write/read operation respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | synchronous DRAM / double data rate / data transfer / skew |
| Paper # | ED98-67,SDM98-67,ICD98-66 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 5GByte/s Data Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM |
| Sub Title (in English) | |
| Keyword(1) | synchronous DRAM |
| Keyword(2) | double data rate |
| Keyword(3) | data transfer |
| Keyword(4) | skew |
| 1st Author's Name | Takashi Sato |
| 1st Author's Affiliation | Semiconductor & Integrated Circuits Division, Hitachi, Ltd.() |
| 2nd Author's Name | Yoji Nishio |
| 2nd Author's Affiliation | Semiconductor & Integrated Circuits Division, Hitachi, Ltd. |
| 3rd Author's Name | Toshio Sugano |
| 3rd Author's Affiliation | Semiconductor & Integrated Circuits Division, Hitachi, Ltd. |
| 4th Author's Name | Yoshinobu Nakagome |
| 4th Author's Affiliation | Semiconductor & Integrated Circuits Division, Hitachi, Ltd. |
| Date | 1998/6/19 |
| Paper # | ED98-67,SDM98-67,ICD98-66 |
| Volume (vol) | vol.98 |
| Number (no) | 121 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |