| Presentation | 1998/6/19 An On-chip Timing Adjuster with Sub-100-ps Resolution for a High-Speed DRAM Interface Hiromasa Noda, Masakazu Aoki, Hitoshi Tanaka, Osamu Nagashima, Hideyuki Aoki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel fully digital fine-delay generator for a high-speed DRAM interface is proposed. The generator consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element(sugeezer)in the delay component converges the variations of the resolution. A testdevice design using 0.35-μm technology demonstrates that a resolution of 26ps can be realized. A timing adjuster using the generator has 2-clock-cycle lock-in time and sub-100-ps error. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-speed DRAM interface / On-chip timing adjuster / Squeezed Array Delay(SQUAD) / Squeezer |
| Paper # | ED98-66,SDM98-66,ICD98-65 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An On-chip Timing Adjuster with Sub-100-ps Resolution for a High-Speed DRAM Interface |
| Sub Title (in English) | |
| Keyword(1) | High-speed DRAM interface |
| Keyword(2) | On-chip timing adjuster |
| Keyword(3) | Squeezed Array Delay(SQUAD) |
| Keyword(4) | Squeezer |
| 1st Author's Name | Hiromasa Noda |
| 1st Author's Affiliation | Semiconductor & IC Division, Hitachi Ltd.() |
| 2nd Author's Name | Masakazu Aoki |
| 2nd Author's Affiliation | Semiconductor & IC Division, Hitachi Ltd. |
| 3rd Author's Name | Hitoshi Tanaka |
| 3rd Author's Affiliation | Hitachi ULSI Systems Co., Ltd. |
| 4th Author's Name | Osamu Nagashima |
| 4th Author's Affiliation | Device Development Center, Hitachi Ltd. |
| 5th Author's Name | Hideyuki Aoki |
| 5th Author's Affiliation | Semiconductor & IC Division, Hitachi Ltd. |
| Date | 1998/6/19 |
| Paper # | ED98-66,SDM98-66,ICD98-65 |
| Volume (vol) | vol.98 |
| Number (no) | 121 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |