| Presentation | 1998/6/19 A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories Tsutomu Yoshimura, Yasunobu Nakase, Naoya Watanabe, Yoshikazu Morooka, Masahiko Hyozo, Yoshio Matsuda, Masaki Kumanoya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an analog DLL for high-speed DDR memories. To minimize jitters, the DLL starts the lock-in process at the minimum delay of the delay line. But this DLL may lose the lock when the temperature increases. A finite-state machine is designed to solve the problem. We also proposes a 90-degree phase shifter with a small offset. The measured static phase offset is less than 120ps at the 2.5V and 800Mbps. This device is fabricated with 0.35μm CMOS technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DLL circuit / Skew control / Lock recovery / Low jitter / Synchronous memory |
| Paper # | ED98-65,SDM98-65,ICD98-64 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories |
| Sub Title (in English) | |
| Keyword(1) | DLL circuit |
| Keyword(2) | Skew control |
| Keyword(3) | Lock recovery |
| Keyword(4) | Low jitter |
| Keyword(5) | Synchronous memory |
| 1st Author's Name | Tsutomu Yoshimura |
| 1st Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Yasunobu Nakase |
| 2nd Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| 3rd Author's Name | Naoya Watanabe |
| 3rd Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corporation |
| 4th Author's Name | Yoshikazu Morooka |
| 4th Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corporation |
| 5th Author's Name | Masahiko Hyozo |
| 5th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| 6th Author's Name | Yoshio Matsuda |
| 6th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| 7th Author's Name | Masaki Kumanoya |
| 7th Author's Affiliation | ULSI Development Center, Mitsubishi Electric Corporation |
| Date | 1998/6/19 |
| Paper # | ED98-65,SDM98-65,ICD98-64 |
| Volume (vol) | vol.98 |
| Number (no) | 121 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |