Presentation 1998/6/19
Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's
Hiroshi Kawaguchi, Yasuhito Itaka, Takayasu Sakurai,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 0.5V SRAM circuit scheme is proposed and fabricated which speeds up the conventional low-voltage SRAM by a factor of 2.5 without applying excessive voltage to gate oxide and with maintaining the subthreshold leakage current in a tolerable level. N-and P-well bias voltage are dynamically changed to V_DD and V_SS respectively for selected memory cells, while the well bias of the dormant memory cells are kept 2V_DD and -V_DD.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) low-voltage SRAM / low-power SRAM / subthreshold leakage current / gate-oxide breakdown voltage / triple-well technology / body-effect
Paper # ED98-62,SDM98-62,ICD98-61
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Conference Date 1998/6/19(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's
Sub Title (in English)
Keyword(1) low-voltage SRAM
Keyword(2) low-power SRAM
Keyword(3) subthreshold leakage current
Keyword(4) gate-oxide breakdown voltage
Keyword(5) triple-well technology
Keyword(6) body-effect
1st Author's Name Hiroshi Kawaguchi
1st Author's Affiliation Institute of Industrial Science, University of Tokyo()
2nd Author's Name Yasuhito Itaka
2nd Author's Affiliation Institute of Industrial Science, University of Tokyo
3rd Author's Name Takayasu Sakurai
3rd Author's Affiliation Institute of Industrial Science, University of Tokyo
Date 1998/6/19
Paper # ED98-62,SDM98-62,ICD98-61
Volume (vol) vol.98
Number (no) 121
Page pp.pp.-
#Pages 4
Date of Issue