Presentation 1998/8/21
A Low Noise CMOS Logic for AD Mixed LSIs
Katsumasa Hijikata, Yoji Kashima, Makoto Nagata, Takashi Morie, Atsushi Iwata,
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Abstract(in English) Currently used CMOS logic gates generate switching noise, when transient current flows through parasitic impedance of a power supply line and a ground line at switching operations. The noise leaks to analog circuits through the substrate and limits their performance, in AD mixed LSIs. The noise consists of two factors, (1) charge and discharge load capacitance and (2) differential response to input/output transitions. we propose a low noise CMOS logic : SCL (Slowly Charging Logic) that supresses noise generation of the first factor. Experimental results of the test chip with 0.35 μm CMOS process technology shows that the peak noise voltage of SCL is around 1/2 and the noise power is around 1/3 compared with those of the conventional CMOS logic.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) AD mixed LSIs / switching noise / substrate noise / SCL
Paper # ICD98-133
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Conference Date 1998/8/21(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Low Noise CMOS Logic for AD Mixed LSIs
Sub Title (in English)
Keyword(1) AD mixed LSIs
Keyword(2) switching noise
Keyword(3) substrate noise
Keyword(4) SCL
1st Author's Name Katsumasa Hijikata
1st Author's Affiliation Faculty of Engineering, Hiroshima University()
2nd Author's Name Yoji Kashima
2nd Author's Affiliation Faculty of Engineering, Hiroshima University
3rd Author's Name Makoto Nagata
3rd Author's Affiliation Faculty of Engineering, Hiroshima University
4th Author's Name Takashi Morie
4th Author's Affiliation Faculty of Engineering, Hiroshima University
5th Author's Name Atsushi Iwata
5th Author's Affiliation Faculty of Engineering, Hiroshima University
Date 1998/8/21
Paper # ICD98-133
Volume (vol) vol.98
Number (no) 245
Page pp.pp.-
#Pages 8
Date of Issue