Presentation 1998/5/22
Basic Theorems for Variable Voltage Low Power Processors
Tohru ISHIHARA, Hiroto YASUURA,
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Abstract(in English) In this paper, we present an integer linear programming (ILP) model for a voltage scheduling problem. In the ILP model, we assume that the core processor can vary its supply voltage dynamically but can use only a single voltage level at a time. The objective function and constraint of ILP problem are energy consumption for given program and execution time, respectively. In addition, we prove basic theorems for variable voltage low power processors. The theorems indicate that the variable voltage scheduling with at most two voltages minimize energy consumption of processor. That is, only a single time voltage alteration while the program is running minimizes energy consumption. These theorems help to keep the energy and timing loss for voltage alteration to the minimum. The theorems must be a guideline to select optimal supply voltages which minimize energy consumption under a timing constraint.
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Keyword(in English) Low power design / Power optimization / Variable voltage / CMOS microprocessor / Hard real-time system
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Conference Date 1998/5/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Basic Theorems for Variable Voltage Low Power Processors
Sub Title (in English)
Keyword(1) Low power design
Keyword(2) Power optimization
Keyword(3) Variable voltage
Keyword(4) CMOS microprocessor
Keyword(5) Hard real-time system
1st Author's Name Tohru ISHIHARA
1st Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University()
2nd Author's Name Hiroto YASUURA
2nd Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University
Date 1998/5/22
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Volume (vol) vol.98
Number (no) 66
Page pp.pp.-
#Pages 8
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