Presentation | 1998/4/24 Bus Instruction Set Computer BISC-1 Kenichi Maruko, Yukihiko Yamashita, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A new architecture of a microprocessor called BISC (Bus Instruction Set Computer) was proposed. This type of processor has instructions only for data transfer between internal registers through internal buses. Therefore, since we don't need to change the instruction set when we add or modify functions of the processor, it has the advantage that various functions can be added easily. Presently, we proceed with logic design of BISC-1 which has a double system and integer bus. In this paper, we explain a basic constitution and specifications of BISC-1 and also describe the way to do arithemetic logic operation, memory access, branch and call. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | microprocessor / architecture / CISC / RISC / BISC |
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Conference Information | |
Committee | ICD |
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Conference Date | 1998/4/24(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Bus Instruction Set Computer BISC-1 |
Sub Title (in English) | |
Keyword(1) | microprocessor |
Keyword(2) | architecture |
Keyword(3) | CISC |
Keyword(4) | RISC |
Keyword(5) | BISC |
1st Author's Name | Kenichi Maruko |
1st Author's Affiliation | Cource of Electrical and Electronic Engineering, Graduate School of Science and Engineering() |
2nd Author's Name | Yukihiko Yamashita |
2nd Author's Affiliation | Department of International Development Engineering, Faculty Engineering Tokyo Institute of Technology |
Date | 1998/4/24 |
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Volume (vol) | vol.98 |
Number (no) | 23 |
Page | pp.pp.- |
#Pages | 8 |
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