Presentation 1995/12/14
Design of Cell Scheduling Chip for ATM networks : An Implementation of Two Step Scheduling Algorithm
Tsuyoshi Takenaka, Juan Noguera Rodriguez, Norio Matsufuru, Kouji Nishimura, Reiji Aibara,
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Abstract(in English) On ATM (Asynchronous Transfer Mode) networks, there are ATM cells categorized ill various traffic classes, e.g., Audio, Movie, IP datagram, etc. However, current implementation of QoS (Quality of Service) of existing products (ATM switches) is restricted, because fast cell scheduler must be required to guarantee the QoS for each traffic class. ATM cell scheduling algorithms are proposed to realize it by ASICs. In this paper, we describe design and evaluation of a cell scheduling chip including "Two Step Scheduling Algorithm".
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Keyword(in English) ATM Network / Cell Scheduling / ASIC / Chip Architecture
Paper # ICD95-186
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Conference Date 1995/12/14(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Cell Scheduling Chip for ATM networks : An Implementation of Two Step Scheduling Algorithm
Sub Title (in English)
Keyword(1) ATM Network
Keyword(2) Cell Scheduling
Keyword(3) ASIC
Keyword(4) Chip Architecture
1st Author's Name Tsuyoshi Takenaka
1st Author's Affiliation Graduate School of Engineering, Hiroshima University()
2nd Author's Name Juan Noguera Rodriguez
2nd Author's Affiliation Graduate School of Engineering, Hiroshima University
3rd Author's Name Norio Matsufuru
3rd Author's Affiliation Graduate School of Engineering, Hiroshima University
4th Author's Name Kouji Nishimura
4th Author's Affiliation Information Processing Center, Hiroshima University
5th Author's Name Reiji Aibara
5th Author's Affiliation Information Processing Center, Hiroshima University
Date 1995/12/14
Paper # ICD95-186
Volume (vol) vol.95
Number (no) 426
Page pp.pp.-
#Pages 6
Date of Issue