Presentation 1995/8/24
Low-Power CMOS and GaAs Digital Design for Multimedia LSIs
Tadayoshi Enomoto,
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Abstract(in English) Techniques are investigated which reduce power dissipation both in CMOS and GaAs digital circuits, while maintaining computational throughput. Common low power techniques for both CMOS and GaAs are (1)lowering power supply voltage, (2)reduction of probability that a power consuming transition occurs (activity factor) and (3)reduction of circuit size. Low power techniques for CMOS are (4)reduction of both signal and clock frequencies and (5)reduction of loading capacitance. Low power technique for GaAs is (4)reduction of direct-path short circuit current. All of above techniques are discussed in detail. In order to drastically reduce power dissipation of LSIs, developments of new architectures, algorithms and fabrication processes are needed, but are very difficult. Although effect is not dramatic, development of low power circuit technologies is the most important way to reduce LSI power consumption.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) multimedia / throughput / power dissipation / CMOS / GaAs / video signal processor
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Conference Date 1995/8/24(1days)
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Language JPN
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Title (in English) Low-Power CMOS and GaAs Digital Design for Multimedia LSIs
Sub Title (in English)
Keyword(1) multimedia
Keyword(2) throughput
Keyword(3) power dissipation
Keyword(4) CMOS
Keyword(5) GaAs
Keyword(6) video signal processor
1st Author's Name Tadayoshi Enomoto
1st Author's Affiliation Dept. of Information and System Engineering Faculty of Science and Engineering Chuo University()
Date 1995/8/24
Paper #
Volume (vol) vol.95
Number (no) 217
Page pp.pp.-
#Pages 13
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