| Presentation | 1995/8/24 A 600mW, Single Chip MPEG2 Video Decoder Hideki Koyanagi, Hiroshi Sumihiro, Seiichi Emoto, Tohru Wada, Tatsuya Sudo, Nozomu Ozaki, Toshirou Ishikawa, Kiyoshi Miura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a 60OmW single-chip MPEG2 video decoder, implemented in a O.5μm triple metal CMOS technology, which operates with a 3.3-volts power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precharge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read power consumption one-third of that of a conventional dual-port RAM. Various techniques such as multiple-clock architecture and a system clock independent from a display clock make a system clock frequency as low as possible. The video decoder has a syntax parser, so that it can handle the higher syntactic elements of MPEG2 bit streams without any host processor and decode Main profile at Main Level of MPEG2 bit streams. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPEG2 / video decoder / low power / dual-port RAM / multiple-clock / asynchronization |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1995/8/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 600mW, Single Chip MPEG2 Video Decoder |
| Sub Title (in English) | |
| Keyword(1) | MPEG2 |
| Keyword(2) | video decoder |
| Keyword(3) | low power |
| Keyword(4) | dual-port RAM |
| Keyword(5) | multiple-clock |
| Keyword(6) | asynchronization |
| 1st Author's Name | Hideki Koyanagi |
| 1st Author's Affiliation | Research Center, Sony Corp.() |
| 2nd Author's Name | Hiroshi Sumihiro |
| 2nd Author's Affiliation | Research Center, Sony Corp. |
| 3rd Author's Name | Seiichi Emoto |
| 3rd Author's Affiliation | Research Center, Sony Corp. |
| 4th Author's Name | Tohru Wada |
| 4th Author's Affiliation | Research Center, Sony Corp. |
| 5th Author's Name | Tatsuya Sudo |
| 5th Author's Affiliation | Research Center, Sony Corp. |
| 6th Author's Name | Nozomu Ozaki |
| 6th Author's Affiliation | Semiconductor Company, Sony Corp. |
| 7th Author's Name | Toshirou Ishikawa |
| 7th Author's Affiliation | Semiconductor Company, Sony Corp. |
| 8th Author's Name | Kiyoshi Miura |
| 8th Author's Affiliation | Research Center, Sony Corp. |
| Date | 1995/8/24 |
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| Volume (vol) | vol.95 |
| Number (no) | 217 |
| Page | pp.pp.- |
| #Pages | 6 |
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