| Presentation | 1995/8/24 A Single Chip, 5GOPS, Macroblock Level Pixel Processor for MPEG2 Encoding. Shinichi Nakagawa, Kiyofumi Kawamoto, Tadao Yamanaka, Haruyuki Ohkuma, Yasue Habara, Shinichi Masuda, Koji Nishigaki, Hiromasa Nakagawa, Kozo Ishida, Atsushi Maeda, Masahiko Yoshimoto, Tadashi Sumi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A single chip ITU-R.601 resolution pixel processing LSI for MPEG2 real-time encoding has been developed. The chip attains 5GOPS performance using a hybrid scheme which is supported by hardwired units and a RISC unit. The RISC unit realizes user-defined adaptive algorithms. A programmable timing scheduling unit provides flexible macroblock-level data flow control. A unique port configuration eliminates pixel transfer bottlenecks to ensure high throughput rate. The chip was fabricated in 0.5μm CMOS double metal technology with 14.54mm x 14.89mm die. It operates at 100MHz and consumes 3.5W at 81MHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPEG2 / Image compression / DCT |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1995/8/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Single Chip, 5GOPS, Macroblock Level Pixel Processor for MPEG2 Encoding. |
| Sub Title (in English) | |
| Keyword(1) | MPEG2 |
| Keyword(2) | Image compression |
| Keyword(3) | DCT |
| 1st Author's Name | Shinichi Nakagawa |
| 1st Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp.() |
| 2nd Author's Name | Kiyofumi Kawamoto |
| 2nd Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 3rd Author's Name | Tadao Yamanaka |
| 3rd Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 4th Author's Name | Haruyuki Ohkuma |
| 4th Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 5th Author's Name | Yasue Habara |
| 5th Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 6th Author's Name | Shinichi Masuda |
| 6th Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 7th Author's Name | Koji Nishigaki |
| 7th Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 8th Author's Name | Hiromasa Nakagawa |
| 8th Author's Affiliation | Mitsubishi Electric Engineering Co., Ltd. |
| 9th Author's Name | Kozo Ishida |
| 9th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 10th Author's Name | Atsushi Maeda |
| 10th Author's Affiliation | Manufacturing Technology Division, Mitsubishi Electric Corp. |
| 11th Author's Name | Masahiko Yoshimoto |
| 11th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 12th Author's Name | Tadashi Sumi |
| 12th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| Date | 1995/8/24 |
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| Volume (vol) | vol.95 |
| Number (no) | 217 |
| Page | pp.pp.- |
| #Pages | 7 |
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