Presentation 1995/5/26
A 35ns-Cycle-Time 3.3V-Only 32Mb NAND Flash EEPROM
Yoshihisa Sugiura, Yoshihisa Iwata, Kenichi Imamiya, Hiroshi Nakamura, Hideko Oodaira, Junichi Miyamoto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 32Mb NAND flash EEPROM has been developed based on 0.425μm CMOS technology. 35ns cycle time for data read-out and programming data load is achieved by adopting a pipeline scheme. A new data-register circuit makes it possible to control programmed cell Vth distribution accurately. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous erase verify for one block reduces total erase time. All functions require only 3.3V power supply.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Flash EEPROM / NAND Type / Pipeline / Bit-by-bit Verify / 3.3V only Power Supply / Erase Verify
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Conference Date 1995/5/26(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 35ns-Cycle-Time 3.3V-Only 32Mb NAND Flash EEPROM
Sub Title (in English)
Keyword(1) Flash EEPROM
Keyword(2) NAND Type
Keyword(3) Pipeline
Keyword(4) Bit-by-bit Verify
Keyword(5) 3.3V only Power Supply
Keyword(6) Erase Verify
1st Author's Name Yoshihisa Sugiura
1st Author's Affiliation Toshiba Corp.()
2nd Author's Name Yoshihisa Iwata
2nd Author's Affiliation Toshiba Corp.
3rd Author's Name Kenichi Imamiya
3rd Author's Affiliation Toshiba Corp.
4th Author's Name Hiroshi Nakamura
4th Author's Affiliation Toshiba Corp.
5th Author's Name Hideko Oodaira
5th Author's Affiliation Toshiba Corp.
6th Author's Name Junichi Miyamoto
6th Author's Affiliation Toshiba Corp.
Date 1995/5/26
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Volume (vol) vol.95
Number (no) 72
Page pp.pp.-
#Pages 6
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