| Presentation | 1995/5/26 A 3.3V Only 16Mb DINOR Flash Memory S. Kobayashi, M. Mihara, Y. Miyawaki, M. Ishii, T. Futatsuya, A. Hosogane, A. Ohba, Y. Terada, N. Ajika, Y. Kunori, M. Hatanaka, H. Miyoshi, T. Yoshihara, Y. Uji, A. Matsuo, Y. Taniguchi, Y. Kiguchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 16M bit 3.3V only DINOR flash memory whose erase unit is 64K byte has been developped. The memory cell size and the chip size are 1.35μm x 1.4 μm and 8.27mm x 9.3mm, respectively. We propose a new program verify scheme which utilizes bit-line shield and high performance positive charge pump circuit utilizing triple well p-n diode which can disregard the body effect of the MOS transistor. Utilizing these technologies, 47ns high speed random access time and 0.8V Vth distribution of the memory cells have been accomplished. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Flash memory / shielded bit line / charge pump / negative voltage control |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1995/5/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 3.3V Only 16Mb DINOR Flash Memory |
| Sub Title (in English) | |
| Keyword(1) | Flash memory |
| Keyword(2) | shielded bit line |
| Keyword(3) | charge pump |
| Keyword(4) | negative voltage control |
| 1st Author's Name | S. Kobayashi |
| 1st Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation() |
| 2nd Author's Name | M. Mihara |
| 2nd Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 3rd Author's Name | Y. Miyawaki |
| 3rd Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 4th Author's Name | M. Ishii |
| 4th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 5th Author's Name | T. Futatsuya |
| 5th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 6th Author's Name | A. Hosogane |
| 6th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 7th Author's Name | A. Ohba |
| 7th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 8th Author's Name | Y. Terada |
| 8th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 9th Author's Name | N. Ajika |
| 9th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 10th Author's Name | Y. Kunori |
| 10th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 11th Author's Name | M. Hatanaka |
| 11th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 12th Author's Name | H. Miyoshi |
| 12th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 13th Author's Name | T. Yoshihara |
| 13th Author's Affiliation | ULSI Laboratory Mitsubishi Electric Corporation |
| 14th Author's Name | Y. Uji |
| 14th Author's Affiliation | Semiconductor & Integrated Circuits Div. Hitachi Ltd. |
| 15th Author's Name | A. Matsuo |
| 15th Author's Affiliation | Semiconductor & Integrated Circuits Div. Hitachi Ltd. |
| 16th Author's Name | Y. Taniguchi |
| 16th Author's Affiliation | Semiconductor & Integrated Circuits Div. Hitachi Ltd. |
| 17th Author's Name | Y. Kiguchi |
| 17th Author's Affiliation | Semiconductor & Integrated Circuits Div. Hitachi Ltd. |
| Date | 1995/5/26 |
| Paper # | |
| Volume (vol) | vol.95 |
| Number (no) | 72 |
| Page | pp.pp.- |
| #Pages | 8 |
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