Presentation 1995/5/26
A 3-GHz CMOS MUX/DEMUX Circuit
Sadayuki Yasuda, Yusuke Ohtomo, Masayuki Ino, Yuichi Kado, Toshiaki Tsuchiya,
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Abstract(in English) A Multiplexer/Demultiplexer(MUX/DEMUX) circuit is a key component for LSIs in high-speed telecommunication systems. We developed a static CMOS circuit technology for a low-power and high-speed MUX/DEMUX circuit. Internal mean capacitance in the double rail flip/flop (DR F/F) is smaller than in single rail one. Because of its symmetric structure, a signal put out from DR F/F is balanced. Having these characteristics, DR F/F is suitable for high speed operation. We designed a 2:1 selector type 4:1 MUX circuit and a 1/2 divider type 1:4 DEMUX circuit with DR F/Fs. Experimental results using 0.25-um SIMOX device process technology show the MUX and DEMUX circuit can respectively operate at 2.98GHz and 4.55GHz at 2.2V supply voltage.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) CMOS / MUX/DEMUX / mean capacitance / phase / DR F/F / 0.25um SIMOX device process technology
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Conference Date 1995/5/26(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 3-GHz CMOS MUX/DEMUX Circuit
Sub Title (in English)
Keyword(1) CMOS
Keyword(2) MUX/DEMUX
Keyword(3) mean capacitance
Keyword(4) phase
Keyword(5) DR F/F
Keyword(6) 0.25um SIMOX device process technology
1st Author's Name Sadayuki Yasuda
1st Author's Affiliation NTT LSI Laboratories()
2nd Author's Name Yusuke Ohtomo
2nd Author's Affiliation NTT LSI Laboratories
3rd Author's Name Masayuki Ino
3rd Author's Affiliation NTT LSI Laboratories
4th Author's Name Yuichi Kado
4th Author's Affiliation NTT LSI Laboratories
5th Author's Name Toshiaki Tsuchiya
5th Author's Affiliation NTT LSI Laboratories
Date 1995/5/26
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Volume (vol) vol.95
Number (no) 72
Page pp.pp.-
#Pages 8
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