| Presentation | 1995/5/26 Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The ringing-canceling output buffer is proposed for low-noise high-speed data transmission. This circuit transmits a two-step pulse so as to cancel the ringing of the received waveform based on the principle of superposition. Simulation results show that this circuit increases the noise margin by a factor of 2.6 compared with the conventional circuit at a data rate of 200MHz. A test circuit is designed and fabricated. The fundamental ringing-canceling effect is experimentally verified. This output buffer is promising for improving the data transfer rate between DRAMs and a microprocessor. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | interface / memory bus / DRAM / noise margin / ringing-canceling output buffer |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1995/5/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer |
| Sub Title (in English) | |
| Keyword(1) | interface |
| Keyword(2) | memory bus |
| Keyword(3) | DRAM |
| Keyword(4) | noise margin |
| Keyword(5) | ringing-canceling output buffer |
| 1st Author's Name | Tomonori Sekiguchi |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Masashi Horiguchi |
| 2nd Author's Affiliation | Semiconductor Development Center, Semiconductor and Integrated Circuits Division, Hitachi, Ltd. |
| 3rd Author's Name | Takeshi Sakata |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 4th Author's Name | Yoshinobu Nakagome |
| 4th Author's Affiliation | Semiconductor Development Center, Semiconductor and Integrated Circuits Division, Hitachi, Ltd. |
| 5th Author's Name | Shigeki Ueda |
| 5th Author's Affiliation | Semiconductor Development Center, Semiconductor and Integrated Circuits Division, Hitachi, Ltd. |
| 6th Author's Name | Masakazu Aoki |
| 6th Author's Affiliation | Memory Business Operation, Semiconductor and Integrated Circuits Division, Hitachi, Ltd. |
| Date | 1995/5/26 |
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| Volume (vol) | vol.95 |
| Number (no) | 72 |
| Page | pp.pp.- |
| #Pages | 6 |
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