| Presentation | 1995/5/25 An NTL-CMOS SRAM Macro Using a CMOS Memory Cell with PMOS Access Transistors Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Toru Yamazaki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An ECL-CMOS SRAM has enabled the ultra high speed and high density features simultaneously. However, it consumes a lot of power and is hard to be applied for a low supply voltage operating application. This paper describes an NTL-CMOS SRAM macro using a CMOS memory cell with PMOS access transistors, an NTL decoder with an on-chip voltage generator and an automatic bit line signal voltage swing controller. A 32Kb SRAM macro has been developed using a 0.4μm BiCMOS technology, which achieves 1ns access time at 2.5V of power supply voltage with 1W power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SRAM / MEMORY CELL / BiCMOS / ECL / NTL / LOW SUPPLY VOLTAGE |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1995/5/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An NTL-CMOS SRAM Macro Using a CMOS Memory Cell with PMOS Access Transistors |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | MEMORY CELL |
| Keyword(3) | BiCMOS |
| Keyword(4) | ECL |
| Keyword(5) | NTL |
| Keyword(6) | LOW SUPPLY VOLTAGE |
| 1st Author's Name | Hitoshi Okamura |
| 1st Author's Affiliation | NEC Corporation System ASIC Department() |
| 2nd Author's Name | Hideo Toyoshima |
| 2nd Author's Affiliation | NEC Microelectronics Research Laboratories |
| 3rd Author's Name | Koichi Takeda |
| 3rd Author's Affiliation | NEC Microelectronics Research Laboratories |
| 4th Author's Name | Takashi Oguri |
| 4th Author's Affiliation | NEC Microelectronics Research Laboratories |
| 5th Author's Name | Satoshi Nakamura |
| 5th Author's Affiliation | NEC Microelectronics Research Laboratories |
| 6th Author's Name | Masahide Takada |
| 6th Author's Affiliation | NEC Microelectronics Research Laboratories |
| 7th Author's Name | Kiyotaka Imai |
| 7th Author's Affiliation | NEC ULSI Device Development Laboratories |
| 8th Author's Name | Yasushi Kinoshita |
| 8th Author's Affiliation | NEC ULSI Device Development Laboratories |
| 9th Author's Name | Hiroshi Yoshida |
| 9th Author's Affiliation | NEC ULSI Device Development Laboratories |
| 10th Author's Name | Toru Yamazaki |
| 10th Author's Affiliation | NEC ULSI Device Development Laboratories |
| Date | 1995/5/25 |
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| Volume (vol) | vol.95 |
| Number (no) | 71 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |