| Presentation | 1993/12/17 Si-on-Si Packaging Technology for Ultra-High-Speed Multi Processor System Kazumichi Miyamoto, Noboru Masuda, Osamu Miura, Kazunori Nakajima, Yuuji Fujita, Satoshi Yoshida, Takao Mori, Kenji Yamaguchi, Mamoru Mita, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Tightyly coupled multi processor system requires high-density packaging technology to reduce interconnection delays between the processor and work storages(secondary caches).So it becomes quite significant to minimize the system controller which connects the processor and the memories.However,the system controller cannot be in one chip because it is difficult to connect thousands of I, O pins.We have proposed a new silicon-on-silicon packaging concept which mounts processor chips and memories on a large-area LSI. Packaging density is greatly improved with this concept. This paper reports newly developed techniques for this concept,a low-resistance wiring technology on the large-area LSI,and an interconnecting method for the large-area LSI. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | silicon-on-silicon packaging / large-area LSI / copper wiring / through wafer interconnection / stacked TAB |
| Paper # | ICD93-155 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1993/12/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Si-on-Si Packaging Technology for Ultra-High-Speed Multi Processor System |
| Sub Title (in English) | |
| Keyword(1) | silicon-on-silicon packaging |
| Keyword(2) | large-area LSI |
| Keyword(3) | copper wiring |
| Keyword(4) | through wafer interconnection |
| Keyword(5) | stacked TAB |
| 1st Author's Name | Kazumichi Miyamoto |
| 1st Author's Affiliation | Central Research Laboratory,Hitachi,Ltd.() |
| 2nd Author's Name | Noboru Masuda |
| 2nd Author's Affiliation | Central Research Laboratory,Hitachi,Ltd. |
| 3rd Author's Name | Osamu Miura |
| 3rd Author's Affiliation | Hitachi Research Laboratory,Hitachi,Ltd. |
| 4th Author's Name | Kazunori Nakajima |
| 4th Author's Affiliation | Central Research Laboratory,Hitachi,Ltd. |
| 5th Author's Name | Yuuji Fujita |
| 5th Author's Affiliation | Central Research Laboratory,Hitachi,Ltd. |
| 6th Author's Name | Satoshi Yoshida |
| 6th Author's Affiliation | Central Research Laboratory,Hitachi,Ltd. |
| 7th Author's Name | Takao Mori |
| 7th Author's Affiliation | Fiberoptics Division,Hitachi,Ltd. |
| 8th Author's Name | Kenji Yamaguchi |
| 8th Author's Affiliation | Systems Material Laboratory,Hitachi Cable,Ltd. |
| 9th Author's Name | Mamoru Mita |
| 9th Author's Affiliation | Densen Works,Hitachi Cable,Ltd. |
| Date | 1993/12/17 |
| Paper # | ICD93-155 |
| Volume (vol) | vol.93 |
| Number (no) | 394 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |