| Presentation | 1993/9/17 Development of a Reconfigurable Parallel Processor for Digital Control Using FPGAs Yoshichika Fujioka, Michitaka Kameyama, Nobuhiro Tomabechi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In digital control,we must reduce the latency for a large number of multiply-additions because of sensor feedback.The reconfigurable parallel VLSI processor is useful for reduction of the latency.In this article,the architecture of the reconfigurable parallel processor using field programmable gate arrays(FPGAs)to verify the VLSI processor design.Although the performance is more drastically improved in the full custom VLSI implementation,even the reconfigurable parallel processor composed of FPGAs becomes useful to many high-performance digital control applications.The performance evaluation shows that the latency for resolved acceleration control computation of a twelve-degrees-of-freedom redundant manipulator becomes about 69 μsec which is about thirty times faster that of a parallel processor approach using conventional digital signal processors(DSPs). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Latency / Digital control / VLSI processor / FPGA / Multi- operand multiply-addition / Reconfiguration |
| Paper # | ICD93-100,DSP93-61 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1993/9/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of a Reconfigurable Parallel Processor for Digital Control Using FPGAs |
| Sub Title (in English) | |
| Keyword(1) | Latency |
| Keyword(2) | Digital control |
| Keyword(3) | VLSI processor |
| Keyword(4) | FPGA |
| Keyword(5) | Multi- operand multiply-addition |
| Keyword(6) | Reconfiguration |
| 1st Author's Name | Yoshichika Fujioka |
| 1st Author's Affiliation | Graduate School of Information Sciences,Tohoku University() |
| 2nd Author's Name | Michitaka Kameyama |
| 2nd Author's Affiliation | Graduate School of Information Sciences,Tohoku University |
| 3rd Author's Name | Nobuhiro Tomabechi |
| 3rd Author's Affiliation | Department of Erectric Engineering,Faculty of Engineering, Hachinohe Institute of Technology |
| Date | 1993/9/17 |
| Paper # | ICD93-100,DSP93-61 |
| Volume (vol) | vol.93 |
| Number (no) | 231 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |