Presentation 1993/9/17
Optical Interconnection Technologies for VLSI Computers
Atsushi Iwata,
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Abstract(in English) With the increase of integration scale in the next decade,the signal delay time and dissipation power of existing ULSIs will be limited by conventional wirings.To overcome these communication crisis,U-OEIC technology which utilizes optical interconnections on a ULSI chip is proposed.This paper presents a model circuit analysis in order to estimate the improvement of delay time and power dissipation in CMOS microprocessors using on-chip optical interconnections for both clock circuits and bus lines.As the results of estimation,the delay time of 20 mm optical interconnection is reduced to 1, 5,and the power dissipation is reduced to 1/5 comparing with the conventional wiring.The machine cycle time and power dissipation of 0.2μm processor will be reduce d to about 1/2.A key fabrication technology of U-OEIC is SI-ULSI compatible processing technology of micron size and low threshold current laser diodes and photo detectors.Furthermore,aiming at 100 fold performance increase,architecture innovation in multi- processors and neural networks is necessary.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Optical Interconnection / Wring Delay / Micro processor / Machine cycle time / Clock Circuit / Bus Line
Paper # ICD93-95,DSP93-56
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Committee ICD
Conference Date 1993/9/17(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optical Interconnection Technologies for VLSI Computers
Sub Title (in English)
Keyword(1) Optical Interconnection
Keyword(2) Wring Delay
Keyword(3) Micro processor
Keyword(4) Machine cycle time
Keyword(5) Clock Circuit
Keyword(6) Bus Line
1st Author's Name Atsushi Iwata
1st Author's Affiliation NTT Electronics Technology Corp.()
Date 1993/9/17
Paper # ICD93-95,DSP93-56
Volume (vol) vol.93
Number (no) 231
Page pp.pp.-
#Pages 8
Date of Issue