Presentation 1993/9/17
Post-Binary Intelligent Integrated Systems
Takahiro Hanyu, Michitaka Kameyama,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Toward the age of ultra-high-density ULSI,multiple-valued digital signal processing will be a key emerging technology in the application to intelligent integrated systems,such as intelligent robot systems,intelligent communication systems,and real-time instrument and control systems.A high degree of spatial parallelism is achieved utilizing the compactness of the multiple- valued arithmetic and logic modules.Moreover,locally computable hardware algorithms and their multiple-valued circuits are very suitable for high-speed signal processing.All the advantages of multiple-valued logic system can be effectively employed for realizing next-generation highly parallel ULSI processor systems. Finally,the effects of hardware algorithms and circuit technologies based on multiple-valued logic are clearly demonstrated in several VLSI processors.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) submicron VLSI / interconnection delay / multiple-valued hardware algorithm / parallel VLSI processor / multiple-valued arithmetic and logic circuits
Paper # ICD93-94,DSP93-55
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Committee ICD
Conference Date 1993/9/17(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Post-Binary Intelligent Integrated Systems
Sub Title (in English)
Keyword(1) submicron VLSI
Keyword(2) interconnection delay
Keyword(3) multiple-valued hardware algorithm
Keyword(4) parallel VLSI processor
Keyword(5) multiple-valued arithmetic and logic circuits
1st Author's Name Takahiro Hanyu
1st Author's Affiliation Tohoku University()
2nd Author's Name Michitaka Kameyama
2nd Author's Affiliation Tohoku University
Date 1993/9/17
Paper # ICD93-94,DSP93-55
Volume (vol) vol.93
Number (no) 231
Page pp.pp.-
#Pages 8
Date of Issue