Presentation 1996/5/24
A 3.3V-only 16GMb Flash Memory with a new Row-Decoding Scheme
Hironori Banba, Akira Umezawa, Masao Kuriyama, Nobuaki Ohtsuka, Naoto Tomita, Yumiko Iyama, Takeshi Miyaba, Ryo Sudo, Eiji Kamiya, Masao Tanimoto, Yohei Hiura, Yoshiko Araki, Eiji Sakagami, Norihisa Arai, Shigeru Atsumi, Seiichi Mori,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 3.3V-only fast random access time 16M flash memory with a new row decoding scheme is developed. This devis is fabiricated using 0.4μm double well CMOS double metal technology. A negative gate biasd erase scheme is implemented to enable 3.3V-only operation. A high performance cherge pump circut is designed for minimize charge pump circuit area. A row decoder circuit with novel level shifter scheme is implemented for stress relaxation during negative gate biased erase operation. A new row redundancy scheme with self-convergence is developed to improve the yied. Quasi-differential sensing with address transition detection is incorporated in the design to obtain fast random access time.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Flash EEPROM / negative gate biased erase / charge pump / 3.3V-only operation
Paper # ICD96-43
Date of Issue

Conference Information
Committee ICD
Conference Date 1996/5/24(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 3.3V-only 16GMb Flash Memory with a new Row-Decoding Scheme
Sub Title (in English)
Keyword(1) Flash EEPROM
Keyword(2) negative gate biased erase
Keyword(3) charge pump
Keyword(4) 3.3V-only operation
1st Author's Name Hironori Banba
1st Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation()
2nd Author's Name Akira Umezawa
2nd Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
3rd Author's Name Masao Kuriyama
3rd Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
4th Author's Name Nobuaki Ohtsuka
4th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
5th Author's Name Naoto Tomita
5th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
6th Author's Name Yumiko Iyama
6th Author's Affiliation Toshiba Microelectronics
7th Author's Name Takeshi Miyaba
7th Author's Affiliation Toshiba Microelectronics
8th Author's Name Ryo Sudo
8th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
9th Author's Name Eiji Kamiya
9th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
10th Author's Name Masao Tanimoto
10th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
11th Author's Name Yohei Hiura
11th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
12th Author's Name Yoshiko Araki
12th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
13th Author's Name Eiji Sakagami
13th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
14th Author's Name Norihisa Arai
14th Author's Affiliation Toshiba Microelectronics
15th Author's Name Shigeru Atsumi
15th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
16th Author's Name Seiichi Mori
16th Author's Affiliation ULSI Device Engineering Laboratory, Toshiba Corporation
Date 1996/5/24
Paper # ICD96-43
Volume (vol) vol.96
Number (no) 65
Page pp.pp.-
#Pages 7
Date of Issue