| Presentation | 1996/9/26 An Analog VLSI Carrying out Image Binarization Hirokuni Fojiyama, Mamoru Sasaki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In a typical image-binaization process, first, an original analog image is converted to the high-resolution digitized image by consuming time and hardware resources for serial scan and 6-8 bits A/D converting every pixel, then, it is converted to the binary image by digital processing. The process seems to be unefficient. This paper describes an analog circuit carrying out binarization process based on least squares criteria. The circuit is integrated on single chip with photosensors in order to directly convert an original analog image to the binary image. The process can overcome an image-reading bottleneck for high-speed image processing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Vision Chip / Analog VLSI / Image Binarization / Least Squares Criteria / Averaging Circuit |
| Paper # | ICD96-115 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1996/9/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Analog VLSI Carrying out Image Binarization |
| Sub Title (in English) | |
| Keyword(1) | Vision Chip |
| Keyword(2) | Analog VLSI |
| Keyword(3) | Image Binarization |
| Keyword(4) | Least Squares Criteria |
| Keyword(5) | Averaging Circuit |
| 1st Author's Name | Hirokuni Fojiyama |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Faculty of Engineering, Kumamoto University() |
| 2nd Author's Name | Mamoru Sasaki |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Faculty of Engineering, Kumamoto University |
| Date | 1996/9/26 |
| Paper # | ICD96-115 |
| Volume (vol) | vol.96 |
| Number (no) | 266 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |