| Presentation | 1996/4/25 PPRAM : A Novel Monolithic-Memory & Multiprocessor ASSP (Application-Specific Standard Product) Architecture Kazuaki MURAKAMI, Shigenobu IWASHITA, Hiroshi MIYAJIMA, Satoru SHIRAKAWA, Takashi YOSHII, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The authors have proposed a new ASSP (Application-Specific Standard Product) architecture, called PPRAM(Parallel Processing Random Access Memory, Practical Parallel Random Access Machine). PPRAMis (i) a monolithic-memory & multiprocessor chip architecture, which integrates multiprocessor and a large size of DRAM on a chip, (ii) a distributed-memory on-chip multiprocessor architecture, which exploits the inherently ultra-high on-chip-memory bandwidth, (iii) a shared-global-register on-chip multiprocessor architecture, which exploits the inherently ultra-low intra-chip communication latency, and (iv) a network-of-chips architecture, which allows scalable computer systems to be made of PPRA Mchips. This paper describes the background of the PPRAM project, the definition of PPRAM, and a hardware/software co-design with PPRAM. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | microprocessor / monolithic memory & logic chip / ASSP / hardware/software co-design |
| Paper # | ICD-96-13,CPSY-96-13,FTS-96-13 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1996/4/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | PPRAM : A Novel Monolithic-Memory & Multiprocessor ASSP (Application-Specific Standard Product) Architecture |
| Sub Title (in English) | |
| Keyword(1) | microprocessor |
| Keyword(2) | monolithic memory & logic chip |
| Keyword(3) | ASSP |
| Keyword(4) | hardware/software co-design |
| 1st Author's Name | Kazuaki MURAKAMI |
| 1st Author's Affiliation | Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University() |
| 2nd Author's Name | Shigenobu IWASHITA |
| 2nd Author's Affiliation | Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University |
| 3rd Author's Name | Hiroshi MIYAJIMA |
| 3rd Author's Affiliation | Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University |
| 4th Author's Name | Satoru SHIRAKAWA |
| 4th Author's Affiliation | Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University |
| 5th Author's Name | Takashi YOSHII |
| 5th Author's Affiliation | Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University |
| Date | 1996/4/25 |
| Paper # | ICD-96-13,CPSY-96-13,FTS-96-13 |
| Volume (vol) | vol.96 |
| Number (no) | 20 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |