| Presentation | 1996/4/25 Design and Implementation of an asynchronous multiplier Masashi Imai, Taro Fujii, Youichirou Ueno, Takashi Nanya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have designed and implemented an asynchronous multiplier using full-custom layout with the objective of verifing the correct implementation and the operation speed of transistor level asynchronous systems. We first describe the chip organization and its operation. Then, the transistor level structure of the full-adder, register, and other components which are used to compose the multiplier are shown. Also, the paper shows that the overall delay of the multiplier circuit designed at transistor level is about 75% compared to the delay of an equivalent circuit, implemented at gate-level. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asynchronous circuit / delay model / request-acknowledge model / differential cascode voltage switch logic |
| Paper # | ICD-96-5,CPSY-96-5,FTS-96-5 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1996/4/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of an asynchronous multiplier |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuit |
| Keyword(2) | delay model |
| Keyword(3) | request-acknowledge model |
| Keyword(4) | differential cascode voltage switch logic |
| 1st Author's Name | Masashi Imai |
| 1st Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Taro Fujii |
| 2nd Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology |
| 3rd Author's Name | Youichirou Ueno |
| 3rd Author's Affiliation | Graduate School of Information Science and Engineering, Tokyo Institute of Technology |
| 4th Author's Name | Takashi Nanya |
| 4th Author's Affiliation | Graduate School of Engineering, Tokyo University |
| Date | 1996/4/25 |
| Paper # | ICD-96-5,CPSY-96-5,FTS-96-5 |
| Volume (vol) | vol.96 |
| Number (no) | 20 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |