| Presentation | 1997/3/7 Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization Takumi Okamoto, Jason Cong, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an efficient algorithm for buffered Steiner tree Construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction, buffer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree construction and dynamic programming based buffer insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the effectiveness of our approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Steiner tree / buffer insertion / wire sizing / timing optimization |
| Paper # | VLD96-107,ICD96-217 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization |
| Sub Title (in English) | |
| Keyword(1) | Steiner tree |
| Keyword(2) | buffer insertion |
| Keyword(3) | wire sizing |
| Keyword(4) | timing optimization |
| 1st Author's Name | Takumi Okamoto |
| 1st Author's Affiliation | C&C Research Laboratories, NEC Corp.() |
| 2nd Author's Name | Jason Cong |
| 2nd Author's Affiliation | Dept. of Computer Science, Univ. of California |
| Date | 1997/3/7 |
| Paper # | VLD96-107,ICD96-217 |
| Volume (vol) | vol.96 |
| Number (no) | 558 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |