Presentation 1997/3/7
Area Minimization for Module Placement Including a Novel Type of Soft-Module
Kunihiro Fujiyoshi, Takeshi Miwa, Hiroshi Murata, Mineo Kaneko,
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Abstract(in English) For a given floorplan which specifies the relative positions of modules, many studies are devoted to determine the widths and the heights of the soft modules to minimize the chip area, subject to preserve the area of each soft module. However, the area of each soft module is not necessarily preserved as far as the total sum of the areas is maintained. For example, a random logic is usually allowed to be divided into a few modules. In this paper, we formulate a new soft module problem for such situation, and give an analytical solution through a proof of a sufficient condition of an optimal solution of the problem.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) soft-module / floorplan / placement / VLSI layout
Paper # VLD96-104,ICD96-214
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Conference Date 1997/3/7(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Area Minimization for Module Placement Including a Novel Type of Soft-Module
Sub Title (in English)
Keyword(1) soft-module
Keyword(2) floorplan
Keyword(3) placement
Keyword(4) VLSI layout
1st Author's Name Kunihiro Fujiyoshi
1st Author's Affiliation Department of Electronic and Information Engineering, Tokyo University of Agriculture & Technology()
2nd Author's Name Takeshi Miwa
2nd Author's Affiliation School of Information Science, Japan Advanced Institute of Science and Technology
3rd Author's Name Hiroshi Murata
3rd Author's Affiliation School of Information Science, Japan Advanced Institute of Science and Technology
4th Author's Name Mineo Kaneko
4th Author's Affiliation School of Information Science, Japan Advanced Institute of Science and Technology
Date 1997/3/7
Paper # VLD96-104,ICD96-214
Volume (vol) vol.96
Number (no) 558
Page pp.pp.-
#Pages 8
Date of Issue