| Presentation | 1997/3/7 Yield Optimization with approximate worst case Hideki Ono, Hidetoshi Onodera, Keikichi Tamaru, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Due to manufacturing process variations, the actual circuit response will be fluctuated on the performance at nominal point. Parametric design process is desirable to have higher yield. Estimating yiled with circuit simulation is very costly process. An approximate worst case design algorithm for parametric yield optimization is presented. In this method, fewer simulation run at one design point achives lower total simulation costs. Additionaly, importance sampling during optimization process reduce simulation runs. Practical example of IC optimization have shown that the algorithm is efficient. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Yield / Optimization / Approximate Worst Case / Analog CAD / Simulation costs |
| Paper # | VLD96-101,ICD96-211 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Yield Optimization with approximate worst case |
| Sub Title (in English) | |
| Keyword(1) | Yield |
| Keyword(2) | Optimization |
| Keyword(3) | Approximate Worst Case |
| Keyword(4) | Analog CAD |
| Keyword(5) | Simulation costs |
| 1st Author's Name | Hideki Ono |
| 1st Author's Affiliation | Graduate School of Engineering, Kyoto University() |
| 2nd Author's Name | Hidetoshi Onodera |
| 2nd Author's Affiliation | Graduate School of Engineering, Kyoto University |
| 3rd Author's Name | Keikichi Tamaru |
| 3rd Author's Affiliation | Graduate School of Engineering, Kyoto University |
| Date | 1997/3/7 |
| Paper # | VLD96-101,ICD96-211 |
| Volume (vol) | vol.96 |
| Number (no) | 558 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |