| Presentation | 1997/3/7 A Fast Resource Allocation Algorithm for Minimizing Interconnection Costs Kenkichi KATO, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a fast resource allocation algorithm for data path design of digital signal processors, whose objective is minimizing interconnection costs of the architecture in reegister-transfer level. The proposed algorithm is composed of (1)register assignment by bipartite weighted matching, (2)functional unit assignment by interconnection probability, and (3)register reassignment by interconnection probability. Since the algorithm takes account of interconnection costs in (1), (2), and (3), it obtains near-optimal solutions in a short time. The experimental results show the effectiveness and efficiency of our algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | digital signal processing / data path design / high-level synthesis / allocation / interconnection costs |
| Paper # | VLD96-96,ICD96-206 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Fast Resource Allocation Algorithm for Minimizing Interconnection Costs |
| Sub Title (in English) | |
| Keyword(1) | digital signal processing |
| Keyword(2) | data path design |
| Keyword(3) | high-level synthesis |
| Keyword(4) | allocation |
| Keyword(5) | interconnection costs |
| 1st Author's Name | Kenkichi KATO |
| 1st Author's Affiliation | Dept. of Electronics and Communication Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Electronics and Communication Engineering, Waseda University |
| 3rd Author's Name | Masao SATO |
| 3rd Author's Affiliation | Dept. of Electronics and Communication Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics and Communication Engineering, Waseda University |
| Date | 1997/3/7 |
| Paper # | VLD96-96,ICD96-206 |
| Volume (vol) | vol.96 |
| Number (no) | 558 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |