Presentation | 1998/3/6 TCAD/DA for ASIC AND MPU Development Hiroo Masuda, Hisako Sato, Katsumi Tsuneno, Kazutaka Mori, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We have proposed, in this paper a, TCAD/DA methodology for MPU and ASIC with updated processes and devises, which allow a predictive chip-design with quick quantitative correlation studies between process-recipe and CKT & delay parameters required in DA works. Effects of statistical process variation on 0.35um CMOS have been rigorously characterized with a new global TCAD calibratoin technique.Based on the deta, process variation effects on a 0.25um CMOS have been predicted, which is concluded that the Vth and Ids total-variation of the 0.25um CMOS shows less than 10% in production process, which is similar with that of the 0.35um CMOS. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Technology-CAD / Design Automation / ASIC / Concurrent Design |
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Conference Information | |
Committee | ICD |
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Conference Date | 1998/3/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | TCAD/DA for ASIC AND MPU Development |
Sub Title (in English) | |
Keyword(1) | Technology-CAD |
Keyword(2) | Design Automation |
Keyword(3) | ASIC |
Keyword(4) | Concurrent Design |
1st Author's Name | Hiroo Masuda |
1st Author's Affiliation | Hitachi, Ltd.() |
2nd Author's Name | Hisako Sato |
2nd Author's Affiliation | Hitachi, Ltd. |
3rd Author's Name | Katsumi Tsuneno |
3rd Author's Affiliation | Hitachi, Ltd. |
4th Author's Name | Kazutaka Mori |
4th Author's Affiliation | Hitachi, Ltd. |
Date | 1998/3/6 |
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Volume (vol) | vol.97 |
Number (no) | 579 |
Page | pp.pp.- |
#Pages | 7 |
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