Presentation 1998/3/5
A Compiler on Synthesis System for Processor Cores of Digital Signal Processing
Takashi KAWASAKI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) This paper proposes a compiler on a hardware/software cosynthesis system which produces processor cores for the digital signal processing.The proposed compiler extracts required hardware units for digital signal processing and paralellization of instructions from the input application program written in C, which can be achieved by assuming that unlimited amount of hardware units can be used. The input application program goes through cmpile templates and thus an assembler code using hardware loop units and addressing units can be generated.As a result, the compiler generates the fastest assembler code in terms of execution clock cycle with the maximum hardware resources of the processor core.Several experimental results show the effectiveness of our compiler.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) compiler / digital signal processing / hardware/software codesign
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Conference Date 1998/3/5(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) A Compiler on Synthesis System for Processor Cores of Digital Signal Processing
Sub Title (in English)
Keyword(1) compiler
Keyword(2) digital signal processing
Keyword(3) hardware/software codesign
1st Author's Name Takashi KAWASAKI
1st Author's Affiliation Dept.of Electronics, Information and Communication Engineering()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept.of Electronics, Information and Communication Engineering
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Dept.of Electronics, Information and Communication Engineering
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept.of Electronics, Information and Communication Engineering
Date 1998/3/5
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Volume (vol) vol.97
Number (no) 578
Page pp.pp.-
#Pages 8
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