| Presentation | 1998/3/5 A Hardware/software Cosynthesis System for Processor Cores of Digital Signal Processing Nozomu TOGAWA, Takashi SAKURAI, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a hardware/software cosynthesis system for processor cores of digital signal processing and a hardware/software partitioning algorithm which is one of the key issues for the system.The target processor has a VLIW-type core which can be composed of a processor kernel, multiple data memory buses(X-bus and Y-bus), hardware loops, addressing units, and multiple functional units.The processor kernel includes five pipeline stages(RISC-type kernel)or three pipeline stages(DSP-type kernel).The system synthesizes a processor core by selecting the required hardware units among them based on a given application program and data and the hardware costs.As a result, the synthesized processor core can range from RISC to DSP.The experimental results show the effectiveness of our system and hardware/software partitioning algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware/software cosynthesis / hardware/software partitioning / processor core / digital signal processing |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1998/3/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware/software Cosynthesis System for Processor Cores of Digital Signal Processing |
| Sub Title (in English) | |
| Keyword(1) | hardware/software cosynthesis |
| Keyword(2) | hardware/software partitioning |
| Keyword(3) | processor core |
| Keyword(4) | digital signal processing |
| 1st Author's Name | Nozomu TOGAWA |
| 1st Author's Affiliation | Dept.of Electronics, Information and Communication Engineering() |
| 2nd Author's Name | Takashi SAKURAI |
| 2nd Author's Affiliation | Dept.of Electronics, Information and Communication Engineering |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept.of Electronics, Information and Communication Engineering |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept.of Electronics, Information and Communication Engineering |
| Date | 1998/3/5 |
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| Volume (vol) | vol.97 |
| Number (no) | 578 |
| Page | pp.pp.- |
| #Pages | 8 |
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