| Presentation | 1998/3/5 Design and Performance Evaluation of a Parallel VLSI Processor for Intelligent Integrated Systems Based on the Dynamic and Static Reconfiguration Yoshichika Fujioka, Nobuhiro Tomabechi, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In intelligent integrated systems such as inteuigent robots, the delay time must be redllced for a large number of multi-operand multiply-additions. To reduce the delay time, the concept of the dynamic reconfiguration of multi-operand multiply-adders, which has the desired number of multipliers, is introduced into the proposed parallel VLSI processor. Moreover, in this paper, to reduce the chip area of the parallel processor and the delay time, the concept of the static reconfiguration of the control circuit is newly introduced. The performance evaluation shows that the delay time for solution of simultaneous linear equations, which is used for manipulator control, becomes about 3 times faster than that of a parallel processor approach using the dynamic reconfiguration method and the very-long-instruction-word control method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | small delay time / multi-operand multiply-addition / FPGA / reconfiguration / hardware subroutine |
| Paper # | |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 1998/3/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Performance Evaluation of a Parallel VLSI Processor for Intelligent Integrated Systems Based on the Dynamic and Static Reconfiguration |
| Sub Title (in English) | |
| Keyword(1) | small delay time |
| Keyword(2) | multi-operand multiply-addition |
| Keyword(3) | FPGA |
| Keyword(4) | reconfiguration |
| Keyword(5) | hardware subroutine |
| 1st Author's Name | Yoshichika Fujioka |
| 1st Author's Affiliation | Department of Electrical Engineering Hachinohe Institute of Technology() |
| 2nd Author's Name | Nobuhiro Tomabechi |
| 2nd Author's Affiliation | Department of Electrical Engineering Hachinohe Institute of Technology |
| Date | 1998/3/5 |
| Paper # | |
| Volume (vol) | vol.97 |
| Number (no) | 578 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |