| Presentation | 1997/10/17 VLSI Architecture for FIR Filter with Very High Throughput While Retaining Small Latency Takeshi Nozaki, Yoshitaka Tsunekawa, Mamoru Miura, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents VLSI architecture for FIR filter with very high throughput while retaining small latency. By using block implementation with characteristic of multirate system, very high throughput becomes possible. Moreover, by using distributed arithmetic, of which processing time depends on only word length, the latency can be minimized. Next, we reveal a new method of lower power dissipation, by making not only the properties of function Φ but also impulse response of even symmetry and odd symmetry. As a result we show that a 32-tap FIR digital filter can be realized with very high sampling rate of 95.2MHz and the small latency of 315ns, by using 0.6μm CMOS technology. In this case, the processor is implemented with relatively low power of 5.41W. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FIR filter / throughput / latency / lower power dissipation / VLSI architecture / VLSI evaluation |
| Paper # | ICD97-159-170 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | VLSI Architecture for FIR Filter with Very High Throughput While Retaining Small Latency |
| Sub Title (in English) | |
| Keyword(1) | FIR filter |
| Keyword(2) | throughput |
| Keyword(3) | latency |
| Keyword(4) | lower power dissipation |
| Keyword(5) | VLSI architecture |
| Keyword(6) | VLSI evaluation |
| 1st Author's Name | Takeshi Nozaki |
| 1st Author's Affiliation | Faculty of Engineering, Iwate University() |
| 2nd Author's Name | Yoshitaka Tsunekawa |
| 2nd Author's Affiliation | Faculty of Engineering, Iwate University |
| 3rd Author's Name | Mamoru Miura |
| 3rd Author's Affiliation | Faculty of Engineering, Iwate University |
| Date | 1997/10/17 |
| Paper # | ICD97-159-170 |
| Volume (vol) | vol.97 |
| Number (no) | 319 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |