| Presentation | 1997/10/17 The Structure of Multiplier for DSP with Complex Arithmetic Capability Yoshimasa NEGISHI, Eiji WATANABE, Akinori NISHIHARA, Takeshi YANAGISAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a method for the effective implementation of specific real coefficient circuits on DSP-C (Digital Signal Processor with Complex arithmetic capability). It is pointed out that higher throughput can be realized by complex multiplications than real ones when implemented circuits have nodes with two input branches. This paper proposes a new structure of complex multipliers for such applications. To implement these multipliers on already-proposed PSI a new operation mode is introduced into PSI, which is named "advanced mode". In the last part of this paper the effectiveness of new PSI is shown by simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital Signal Processor / Simulator / 2D circuit / Transversal circuit / Butterfly |
| Paper # | ICD97-159-170 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Structure of Multiplier for DSP with Complex Arithmetic Capability |
| Sub Title (in English) | |
| Keyword(1) | Digital Signal Processor |
| Keyword(2) | Simulator |
| Keyword(3) | 2D circuit |
| Keyword(4) | Transversal circuit |
| Keyword(5) | Butterfly |
| 1st Author's Name | Yoshimasa NEGISHI |
| 1st Author's Affiliation | Faculty of Systems Engineering, Shibaura Institute of Technology() |
| 2nd Author's Name | Eiji WATANABE |
| 2nd Author's Affiliation | Faculty of Systems Engineering, Shibaura Institute of Technology |
| 3rd Author's Name | Akinori NISHIHARA |
| 3rd Author's Affiliation | The Center for Research and Development of Educational Technology, Tokyo Institute of Technology |
| 4th Author's Name | Takeshi YANAGISAWA |
| 4th Author's Affiliation | Faculty of Systems Engineering, Shibaura Institute of Technology |
| Date | 1997/10/17 |
| Paper # | ICD97-159-170 |
| Volume (vol) | vol.97 |
| Number (no) | 319 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |