Presentation | 1997/9/26 Adiabatic Dynamic CMOS Logic Circuit Kazukiyo TAKAHASHI, Kentaro OZAWA, Mitsuru MIZUNUMA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Adiabatic dynamic CMOS logic (ADCL) circuit has been proposed for an ultra low power logic circuit. Availability of the ADCL is confirmed by the circuit analysis, computer simulation and experimentation using discrete components. Simplicity of the logic interconnection is nearly as same as CMOS logic. However, energy consumption of the ADCL circuit is almost 2 order less than CMOS logic. For the ADCL inverter loaded with a 0.1pF capacitor using W/L = 10p/1.5μ MOSFET's, it has been shown by computer simulation that the energy dissipation per operation is 0.39pJ if the supply voltage is 5V_ |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Adiabatic logic / Adiabatic dynamic CMOS logic / Dynamic logic / Energy dissipation |
Paper # | ICD97-145 |
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Committee | ICD |
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Conference Date | 1997/9/26(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Adiabatic Dynamic CMOS Logic Circuit |
Sub Title (in English) | |
Keyword(1) | Adiabatic logic |
Keyword(2) | Adiabatic dynamic CMOS logic |
Keyword(3) | Dynamic logic |
Keyword(4) | Energy dissipation |
1st Author's Name | Kazukiyo TAKAHASHI |
1st Author's Affiliation | Yamagata University, Faculty of Engineering() |
2nd Author's Name | Kentaro OZAWA |
2nd Author's Affiliation | Yamagata University, Faculty of Engineering |
3rd Author's Name | Mitsuru MIZUNUMA |
3rd Author's Affiliation | Yamagata University, Faculty of Engineering |
Date | 1997/9/26 |
Paper # | ICD97-145 |
Volume (vol) | vol.97 |
Number (no) | 275 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |