Presentation 1997/9/26
Single-Electron Majority Logic Circuits
Hiroki IWAMURA, Masamichi AKAZAWA, Yoshihito AMEMIYA,
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Abstract(in English) This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) majority logic / single electron / gate / adder / noise
Paper # ICD97-139
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Committee ICD
Conference Date 1997/9/26(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Single-Electron Majority Logic Circuits
Sub Title (in English)
Keyword(1) majority logic
Keyword(2) single electron
Keyword(3) gate
Keyword(4) adder
Keyword(5) noise
1st Author's Name Hiroki IWAMURA
1st Author's Affiliation Faculty of Engineerring, Hokkaido University()
2nd Author's Name Masamichi AKAZAWA
2nd Author's Affiliation Faculty of Engineerring, Hokkaido University
3rd Author's Name Yoshihito AMEMIYA
3rd Author's Affiliation Faculty of Engineerring, Hokkaido University
Date 1997/9/26
Paper # ICD97-139
Volume (vol) vol.97
Number (no) 275
Page pp.pp.-
#Pages 6
Date of Issue