Presentation 1997/9/26
Analysis of GaAs HJFET Mark Ratio Effect with Device Simulator for Cyclic Bias Application
Yuji Takahashi, Kazuaki Kunihiro, Yasuo Ohno,
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Abstract(in English) A two-dimensional device simulator for analyzing the steady-state of devices under cyclic bias application has been developed. With this simulator, we can simulate the steady state under the cyclic bias, which is used in normal device evaluation. Application of the simulator to the pulse-pattern effect of a GaAs HJFET showed that the low- and high-level drain currents varied with the mark ratio. These variations showed a non-linearity that became more significant as the pulse-amplitude increased. Thdse variations can be explained by SRH statistics model for the deep-level traps.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Device Simulator / Mark ratio Effect / Cyclic Bias / SRH statistics / HJFET
Paper # ICD97-138
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Conference Date 1997/9/26(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analysis of GaAs HJFET Mark Ratio Effect with Device Simulator for Cyclic Bias Application
Sub Title (in English)
Keyword(1) Device Simulator
Keyword(2) Mark ratio Effect
Keyword(3) Cyclic Bias
Keyword(4) SRH statistics
Keyword(5) HJFET
1st Author's Name Yuji Takahashi
1st Author's Affiliation Opto Electronics and High Frequency Device Research Lab., NEC Corp.()
2nd Author's Name Kazuaki Kunihiro
2nd Author's Affiliation Opto Electronics and High Frequency Device Research Lab., NEC Corp.
3rd Author's Name Yasuo Ohno
3rd Author's Affiliation Opto Electronics and High Frequency Device Research Lab., NEC Corp.
Date 1997/9/26
Paper # ICD97-138
Volume (vol) vol.97
Number (no) 275
Page pp.pp.-
#Pages 6
Date of Issue