| Presentation | 1997/8/22 A 4.25GHz BiCMOS Clock Recovery Circuit with an AV-DSPD Architecture for NRZ Data Stream Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An AV-DSPD architecture to achieve an operation frequency two times higher than that of an internal phase detector is proposed, which limits the conventional clock recovery circuit (CRC). A VCO of the CRC is controlled by the absolute value of divided signal phase differences (AV-DSPD). Based of the AV-DSPD architecture, a 4.25GHz CRC suitable for NRZ data stream has been developed using BiCMOS technology. Peak to peak jitter of the recovered 4.25GHz clock is 40ps, power consumption is 150mW at 3.3V supply voltage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | clock recovery PLL / divided signal / absolute value / 0.25μm BICMOS |
| Paper # | ICD97-117 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/8/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 4.25GHz BiCMOS Clock Recovery Circuit with an AV-DSPD Architecture for NRZ Data Stream |
| Sub Title (in English) | |
| Keyword(1) | clock recovery PLL |
| Keyword(2) | divided signal |
| Keyword(3) | absolute value |
| Keyword(4) | 0.25μm BICMOS |
| 1st Author's Name | Muneo Fukaishi |
| 1st Author's Affiliation | Silicon Systems Research Labs., NEC Corporation() |
| 2nd Author's Name | Satoshi Nakamura |
| 2nd Author's Affiliation | ULSI Device Development Labs., NEC Corporation |
| 3rd Author's Name | Akio Tajima |
| 3rd Author's Affiliation | C&C Media Research Labs., NEC Corporation |
| 4th Author's Name | Yasushi Kinoshita |
| 4th Author's Affiliation | ULSI Device Development Labs., NEC Corporation |
| 5th Author's Name | Yoshihiko Suemura |
| 5th Author's Affiliation | C&C Media Research Labs., NEC Corporation |
| 6th Author's Name | Hisamitsu Suzuki |
| 6th Author's Affiliation | ULSI Device Development Labs., NEC Corporation |
| 7th Author's Name | Toshiro Itani |
| 7th Author's Affiliation | ULSI Device Development Labs., NEC Corporation |
| 8th Author's Name | Hidenobu Miyamoto |
| 8th Author's Affiliation | ULSI Device Development Labs., NEC Corporation |
| 9th Author's Name | Naoya Henmi |
| 9th Author's Affiliation | C&C Media Research Labs., NEC Corporation |
| 10th Author's Name | Tohru Yamazaki |
| 10th Author's Affiliation | ULSI Device Development Labs., NEC Corporation |
| 11th Author's Name | Michio Yotsuya |
| 11th Author's Affiliation | Silicon Systems Research Labs., NEC Corporation |
| Date | 1997/8/22 |
| Paper # | ICD97-117 |
| Volume (vol) | vol.97 |
| Number (no) | 230 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |