| Presentation | 1997/8/22 Trellis-coded PRML read-channel LSI for HDD Norio Shoji, Yoshihiro Komatsu, Shinichi Watanabe, Masafumi Yamashita, Yuji Gendai, Katsuyuki Yonezawa, Kimimasa Senba, Hiroyuki Akahoshi, Nobuhiro Hayashi, Yoshiharu Shimano, Masaki Uchida, Hiroaki Yada, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A PRML read-channel LSI for HDD that adapts rate 8/10 partitioned matched spectral null code is successfully developed. The code has 3 dB advantage over the conventional PR4ML, enabling higher recording density. Multi-chip module implementation allowed to use up-to-date processes both in analog and digital sections. The partial response equalizer consists of two parts: a new topology 7-pole 2-zero equi-ripple analog filter and a 3-tap FIR adaptive digital filter. The former realizes sufficient equalization while the latter absorbs the media variation. The clock recovery PLL is devised to have constant 4 and proportional ωn to data rate. The bipolar chip is 28.6k elements, 3.88×6.28 mm^2 and 580mW. The CMOS chip is 41k gates, 2.27×5.37mm^2 and 270mW@100MHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | trellis code / MSN code / PRML / filter / PLL / signal processing |
| Paper # | ICD97-113 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/8/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Trellis-coded PRML read-channel LSI for HDD |
| Sub Title (in English) | |
| Keyword(1) | trellis code |
| Keyword(2) | MSN code |
| Keyword(3) | PRML |
| Keyword(4) | filter |
| Keyword(5) | PLL |
| Keyword(6) | signal processing |
| 1st Author's Name | Norio Shoji |
| 1st Author's Affiliation | Sony Corporation() |
| 2nd Author's Name | Yoshihiro Komatsu |
| 2nd Author's Affiliation | Sony Corporation |
| 3rd Author's Name | Shinichi Watanabe |
| 3rd Author's Affiliation | Sony Corporation |
| 4th Author's Name | Masafumi Yamashita |
| 4th Author's Affiliation | Sony Corporation |
| 5th Author's Name | Yuji Gendai |
| 5th Author's Affiliation | Sony Corporation |
| 6th Author's Name | Katsuyuki Yonezawa |
| 6th Author's Affiliation | Sony Corporation |
| 7th Author's Name | Kimimasa Senba |
| 7th Author's Affiliation | Sony Corporation |
| 8th Author's Name | Hiroyuki Akahoshi |
| 8th Author's Affiliation | Sony Kokubu Corporation |
| 9th Author's Name | Nobuhiro Hayashi |
| 9th Author's Affiliation | Sony Corporation |
| 10th Author's Name | Yoshiharu Shimano |
| 10th Author's Affiliation | Sony Corporation |
| 11th Author's Name | Masaki Uchida |
| 11th Author's Affiliation | Sony Corporation |
| 12th Author's Name | Hiroaki Yada |
| 12th Author's Affiliation | Sony Corporation |
| Date | 1997/8/22 |
| Paper # | ICD97-113 |
| Volume (vol) | vol.97 |
| Number (no) | 230 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |