Presentation 1997/8/22
A Macroscopic Substrate Noise Model for Full Chip Mixed-Signal Design Verification
Makoto Nagata, Yasuhiro Yamamoto, Atsushi Iwata,
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Abstract(in English) A macroscopic substrate noise model is proposed and implemented in the mixed signal simulation environment. The model enables full chip verification of the substrate noise effect on chip performance in mixed-signal VLSIs. The model describes the substrate noise in AnalogHDL as a continuous function of transition probabilities in the digital partitions. Performance degradation of 2nd order ΔΣADC due to the noise is clearly simulated by transient analysis.
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Keyword(in English) Mixed Signal LSI / Cross Talk Noise / AnalogHDL / Mixed Signal Simulation / ΔΣADC
Paper # ICD97-111
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Conference Date 1997/8/22(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Macroscopic Substrate Noise Model for Full Chip Mixed-Signal Design Verification
Sub Title (in English)
Keyword(1) Mixed Signal LSI
Keyword(2) Cross Talk Noise
Keyword(3) AnalogHDL
Keyword(4) Mixed Signal Simulation
Keyword(5) ΔΣADC
1st Author's Name Makoto Nagata
1st Author's Affiliation Faculty of Engineering, Hiroshima University()
2nd Author's Name Yasuhiro Yamamoto
2nd Author's Affiliation Faculty of Engineering, Hiroshima University
3rd Author's Name Atsushi Iwata
3rd Author's Affiliation Faculty of Engineering, Hiroshima University
Date 1997/8/22
Paper # ICD97-111
Volume (vol) vol.97
Number (no) 230
Page pp.pp.-
#Pages 8
Date of Issue