Presentation 1997/8/22
A Comparison of Noise Generation of Various Logics in CMOS A-D mixed LSI's
Katsumasa Hijikata, Yoji Kashima, Makoto Nagata, Atsushi Iwata,
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Abstract(in English) Currently used CMOS logic gates generate large noise by transient current at switching operations. This noise limits analog circuit performance in A-D mixed LSIs, because it transfers to analog circuits through a substrate. We have studied characteristics as noise sources of Current Steering Logic:CSL, Current Mode Logic:CML which operate with constant supply currents. By SPICE simulations and experiments of the test chip with 0.6μm CMOS technology, the noise amounts of these logics were evaluated. We have found that (1) simulated noise amounts of CSL and CML are around 1/2 and 1/10 compared with CMOS, respectively, and (2) measured substrate noise amounts are around 1/3 and 1/7.
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Keyword(in English) A-D mixed LSI / switching noise / crosstalk noise / CSL / CML
Paper # ICD97-109
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Conference Date 1997/8/22(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Comparison of Noise Generation of Various Logics in CMOS A-D mixed LSI's
Sub Title (in English)
Keyword(1) A-D mixed LSI
Keyword(2) switching noise
Keyword(3) crosstalk noise
Keyword(4) CSL
Keyword(5) CML
1st Author's Name Katsumasa Hijikata
1st Author's Affiliation Faculty of Engineering, Hiroshima University()
2nd Author's Name Yoji Kashima
2nd Author's Affiliation Faculty of Engineering, Hiroshima University
3rd Author's Name Makoto Nagata
3rd Author's Affiliation Faculty of Engineering, Hiroshima University
4th Author's Name Atsushi Iwata
4th Author's Affiliation Faculty of Engineering, Hiroshima University
Date 1997/8/22
Paper # ICD97-109
Volume (vol) vol.97
Number (no) 230
Page pp.pp.-
#Pages 8
Date of Issue