Presentation 1997/8/22
A PWM Signal Multiply-Accumulate Circuit using a Charge Packet Counting Technique
Daisuke Nomasaki, Takahiro Yoneda, Makoto Nagata, Atsushi Iwata,
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Abstract(in English) As for a multiply-accumulation (MAC) of parallel PWM signals based on the switched current integration technique, its operation scale is limited by the range of linear integration voltage. A 0.8umCMOS PWM-MAC is designed on the basis of a charge Packet Counting technique where integration charge is transformed into a pulse in every charge reference. The technique resolves the above problem and test chip demonstrates more than 20V of equivalent integration voltage and 8bit accuracy.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Switched Current Integration Technique / Analog Digital merged circuit / CPC / PWM / MAC
Paper # ICD97-108
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Conference Date 1997/8/22(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A PWM Signal Multiply-Accumulate Circuit using a Charge Packet Counting Technique
Sub Title (in English)
Keyword(1) Switched Current Integration Technique
Keyword(2) Analog Digital merged circuit
Keyword(3) CPC
Keyword(4) PWM
Keyword(5) MAC
1st Author's Name Daisuke Nomasaki
1st Author's Affiliation Faculty of Engineering, Hiroshima University()
2nd Author's Name Takahiro Yoneda
2nd Author's Affiliation Faculty of Engineering, Hiroshima University
3rd Author's Name Makoto Nagata
3rd Author's Affiliation Faculty of Engineering, Hiroshima University
4th Author's Name Atsushi Iwata
4th Author's Affiliation Faculty of Engineering, Hiroshima University
Date 1997/8/22
Paper # ICD97-108
Volume (vol) vol.97
Number (no) 230
Page pp.pp.-
#Pages 8
Date of Issue