| Presentation | 1997/6/20 Low-Voltage 0.35μm CMOS/SOI Technology for High-Performance ASIC's T Naka, A. O. Adan, S Kaneko, D. Urabe, K. Higashi, A. Kagisawa, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We describe a 0.35μm CMOS Process technology for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIM0X) wafers. Stable high speed, Low-Vth transistors for low-voltage operation at 1.5V were developed by integrating a salicided dual gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6GHz at 1.5V supply voltage, demonstrating the excellent performance of this technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-performance ASIC's / Shallow SIMOX / Low-voltage operation / Salicide / Dual-gate |
| Paper # | ED97-54 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Voltage 0.35μm CMOS/SOI Technology for High-Performance ASIC's |
| Sub Title (in English) | |
| Keyword(1) | High-performance ASIC's |
| Keyword(2) | Shallow SIMOX |
| Keyword(3) | Low-voltage operation |
| Keyword(4) | Salicide |
| Keyword(5) | Dual-gate |
| 1st Author's Name | T Naka |
| 1st Author's Affiliation | SHARP Corp., IC Group, VLSI Devel. Lab.() |
| 2nd Author's Name | A. O. Adan |
| 2nd Author's Affiliation | SHARP Corp., IC Group, VLSI Devel. Lab. |
| 3rd Author's Name | S Kaneko |
| 3rd Author's Affiliation | SHARP Corp., IC Group, VLSI Devel. Lab. |
| 4th Author's Name | D. Urabe |
| 4th Author's Affiliation | SHARP Corp., IC Group, VLSI Devel. Lab. |
| 5th Author's Name | K. Higashi |
| 5th Author's Affiliation | SHARP Corp., IC Group, VLSI Devel. Lab. |
| 6th Author's Name | A. Kagisawa |
| 6th Author's Affiliation | SHARP Corp., IC Group, VLSI Devel. Lab. |
| Date | 1997/6/20 |
| Paper # | ED97-54 |
| Volume (vol) | vol.97 |
| Number (no) | 111 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |