Presentation | 1997/6/20 A1-V Battery Operated 0.25-μm SRAM Macrocell for Portable Equipment Nobutaro SHIBATA, Hiroki MORIMURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | SRAM macrocell techniques for 1-V battery operated ASIC's are described. To shorten the bitline delay at reading data, a memory cell configuration using an accelerator by low-threshold-voltage MOSFET's is proposed. Also, bitline-multiplexer-merged high-speed sense amplifier is proposed. To write data with a short delay time, write buffers are connected to bitlines with no bitline multiplexer. The power dissipation of address decoder is reduced using block selection signals, which are obtained by decoding higher group of address signals. An SRAM test chip fabricated with 0.25-μm MTCMOS technology has demonstrated the feasibility of 100-MHz operation at a 1-V power supply. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | low voltage / 1-V / Ni-Cd battery cell / SRAM / low power / fast |
Paper # | ED97-52 |
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Conference Information | |
Committee | ICD |
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Conference Date | 1997/6/20(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A1-V Battery Operated 0.25-μm SRAM Macrocell for Portable Equipment |
Sub Title (in English) | |
Keyword(1) | low voltage |
Keyword(2) | 1-V |
Keyword(3) | Ni-Cd battery cell |
Keyword(4) | SRAM |
Keyword(5) | low power |
Keyword(6) | fast |
1st Author's Name | Nobutaro SHIBATA |
1st Author's Affiliation | NTT System Electronics Laboratories() |
2nd Author's Name | Hiroki MORIMURA |
2nd Author's Affiliation | NTT System Electronics Laboratories |
Date | 1997/6/20 |
Paper # | ED97-52 |
Volume (vol) | vol.97 |
Number (no) | 111 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |